Multi-layer interconnection circuit module and manufacturing method thereof

ABSTRACT

The present invention is directed to a multi-layer interconnection circuit module in which plural unit wiring layers are interlayer-connected to each other through a large number of via holes so that they are laminated and formed, wherein respective unit wiring layers ( 8 ) to ( 12 ) are adapted so that photo-lithographic processing is implemented to a first insulating layer ( 22 ) formed by photosensitive insulating resin material to form via hole grooves ( 25 ), and photo-lithographic processing is implemented to a second insulating layer ( 23 ) formed by photosensitive insulating resin material on the first insulating layer ( 22 ) to form wiring grooves ( 27 ). A conductive metal layer ( 24 ) is formed on the second insulating layer ( 23 ) in such a manner that conductive metal is filled within the via hole grooves ( 25 ) and the wiring grooves ( 27 ) to implement polishing processing to the conductive metal layer ( 24 ) until the principal surface of the second insulating layer ( 23 ) is exposed to form via holes ( 13 ) and wiring patterns ( 26 ) by the conductive metal filled within the via hole grooves ( 25 ) and the wiring grooves ( 27 ).

TECHNICAL FIELD

The present invention relates to a multi-layer interconnection circuitmodule in which thin structure and high density wiring have beenrealized, and a manufacturing method thereof.

This Application claims priority of Japanese Patent Application No.2002-195018, field on Jul. 3, 2002, the entirety of which isincorporated by reference herein.

BACKGROUND ART

In various digital electronic equipments, e.g., personal computer,mobile telephone, video equipment and/or audio equipment, etc., there isprovided multi-chip circuit module on which semiconductor chips such asvarious IC elements or LSI elements, etc. are mounted. In variousdigital electronic equipments, finning of circuit pattern,miniaturization of IC package, rapid improvement in integration scale,multi-pin structure and/or improvement in mounting method, etc. havebeen provided so that miniaturization and high level function of themulti-chip circuit module are realized. Thus, miniaturization and lightweight, and/or thin structure are realized, and high performance, highlevel function, multi-function and/or high speed processing, etc. havebeen realized.

In multi-chip circuit modules, there are also circuit modules where theso-called system LSI on which circuits having different functions, e.g.,logic function and memory function or analog function and digitalfunction, etc. are mounted are constituted. In the multi-chip circuitmodules, there are also circuit modules in which the so-calledmulti-chip circuit module where functional blocks of respectiveprocesses are manufactured as individual semiconductor chips and thesesemiconductor chips are mounted on the same board is constituted.

Meanwhile, in the multi-chip circuit module, in order to realize furtherimprovement in performance, realization of high speed of microprocessorand/or realization of high density of signal wiring between memory chipsare required, and it is necessary to take a measure for the problem ofwiring delay. In the multi-chip circuit module, even if clock frequencyabove GHz is realized within respective elements (chips), clockfrequency must be lowered in digit units owing to the problems such assignal delay and/or reflection, etc. based on wirings between chips. Inaddition, in the multi-chip circuit module, realization of high speed ofsignal wiring and/or realization of high density are provided to therebyalso require countermeasure for, e.g., EMI (electromagneticinterference) or EMC (electromagnetic compatibility). Accordingly, inthe multi-chip circuit module, it is necessary to provide realization ofhigh integration and/or high performance on the whole as a systemtechnology including mounting technology for package or board, etc. inaddition to improvement in formation technology for chip.

Hitherto, as the multi-chip circuit module, there is a circuit module asshown in FIG. 1. The circuit module shown in FIG. 1 is a multi-chipcircuit module 100 of the flip-chip type in which plural semiconductorchips 102A, 102B are mounted on a principal surface 101 a of aninterposer 101. The multi-chip circuit module 100 is adapted so thatsuitable circuit patterns, lands and/or input/output terminals, etc. arerespectively formed on the surface principal surface 101 a and the backprincipal surface 101 b of the interposer 101 are formed. In themulti-chip circuit module 100, at the principal surface 101 a of theinterposer 101, respective semiconductor chips 102 are mounted in thestate where they are respectively flip-chip connected on predeterminedlands 103 and connecting portions are covered by underfill 104 on theprincipal surface 101 a of the interposer 101. At the multi-chip circuitmodule 100, solder balls 105 are respectively mounted at lands formed atthe principal surface 101 b of the interposer 101, and reflow solderprocessing is implemented in the state where they are mounted on, e.g.,mother board, etc. to melt and solidify the solder balls 105. Thus, themulti-chip circuit module is mounted.

As described above, at the conventional multi-chip circuit module 100,plural semiconductor chips 102 are mounted in lateral arrangement stateon the principal surface 101 a of the interposer 101. However, wiringswhich connect respective semiconductor chips 102 are restricted bycircuit patterns formed at the interposer 101 side. In the multi-chipcircuit module 100, with realization of multi-function and realizationof high speed, etc. of the apparatus where this module 100 is mounted, alarge number of semiconductor chips 102 are provided. Thus, a largernumber of wirings are required. In the multi-chip circuit module 100,because pitch of wiring pattern formed at the interposer 101manufactured by the general board (substrate) manufacturing technologyis large value of the order of about 100 μm even at the minimum byrestriction of manufacturing condition, etc., interposer 101 of largearea or caused to be of multi-layer structure is required in the casewhere a large number of connections are made between pluralsemiconductor chips 102.

In the multi-chip circuit module 100, in the case where multi-layeredinterposer 101 is used, interlayer connection through via and/orconnection between respective semiconductor chips 102 are conducted. Inthis case, since its hole diameter is about 50 μm even at the minimumfrom the processing condition, and land diameter is also about 50 μmeven at the minimum, large-sized interposer 101 is required. For thisreason, at the multi-chip circuit module 100, there were the problemsthat wiring pattern formed at the interposer 101 which connectsrespective semiconductor chips 102 is elongated, and many vias areformed so that L-C-R components become large.

For example, in the manufacturing process for the semiconductor device,there has been also proposed a technology in which an insulating layeris formed as film on a silicon substrate thereafter to form fine wiringpattern via dry etching step of forming via grooves and wiring groovesand film formation step for conductive metal layer. In such wiringformation method, first dry etching processing is implemented to aninsulating layer to form a large number of via grooves, and second dryetching processing is implemented to form wiring grooves as pattern. Inthis wiring formation method, copper film layer is formed by, e.g.,plating on the entire surface of the insulating layer thereafter toimplement polishing processing to this copper film layer to thereby formvia holes and a predetermined wiring pattern.

In accordance with such wiring formation method, as compared to thetypical wiring formation method of forming via holes by machining orlaser processing and implementing etching processing to copper foil toform circuit pattern, it is possible to form fine and high densitywiring pattern as multi-layer structure. In this wiring formationmethod, it is necessary to implement precise first dry etchingprocessing and precise second dry etching processing having depths ofgroove different from each other, and it is difficult to apply thismethod to manufacturing process for typical multi-layer wiring board. Inaddition, in accordance with this wiring formation method, since wiringlayers are formed on silicon substrate as multi-layer structure, thereare the problem that the mounting structure onto mother board, etc.becomes complicated so that realization of miniaturization becomesdifficult, and wiring pattern is also elongated.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a novel multi-layerinterconnection (wiring) circuit module and a manufacturing methodthereof which can solve problems that conventional multi-chip circuitmodules as described above have.

Another object of the present invention is to provide a multi-layerinterconnection (wiring) circuit module and a manufacturing methodthereof in which respective unit wiring layers have fine and highdensity wiring patterns and have Via-on-Via structure so that interlayerconnection is conducted by the shortest wiring length, miniaturizationand thin structure can be realized, and high speed processing andimprovement in reliability can be realized.

A multi-layer interconnection circuit module according to the presentinvention is adapted so that plural unit wiring layers areinterlayer-connected through a large number of via holes so that theyare laminated, wherein each unit wiring layer is composed of a firstinsulating layer, a second insulating layer, and a conductive metalliclayer to which polishing processing is implemented. The first insulatinglayer is formed as film by photosensitive insulating resin material, andphoto-lithographic processing is implemented so that a large number ofvia hole grooves corresponding to respective via holes are formed. Thesecond insulating layer is formed as film by photosensitive insulatingresin material on the first insulating layer, and photo-lithographicprocessing is implemented so that communicating portions with respectivevia hole grooves provided at a portion thereof and wiring groovescorresponding to wiring patterns are formed as pattern. The conductivemetallic layer is formed as film over the entire surface of the secondinsulating layer in the state where conductive metal is filled alsowithin respective via hole grooves and wiring grooves. Polishingprocessing is implemented to respective unit wiring layers until theprincipal surface of the second insulating layer is exposed so thatrespective via holes and wiring patterns are formed by conductive metalfilled within respective via hole grooves and wiring grooves of theconductive metallic layer exposed in such a manner to constitute thesame surface on the principal surface of the second insulating layer.

In accordance with the multi-layer interlayer circuit module accordingto the present invention, photo-lithographic processing by simpleequipment and work are respectively implemented to the first and secondinsulating layers formed as film by photosensitive insulating resinmaterial to form via hole grooves and wiring grooves which have highresolution. From this fact, it becomes possible to form micro via holesand/or fine and high density wiring pattern. In accordance with themulti-layer interconnection (wiring) circuit module, respective unitwiring layers are interlayer-connected to each other at the shortestdistance by Via-on-Via structure so that they are laminated and formedto thereby shorten wiring length. As a result, attenuation of signalscaused to undergo transmission is reduced, and signal delay isminimized. In addition, thin structure is realized, thus making itpossible to cope with, e.g., large capacity, high speed and high densitybus.

A method of manufacturing multi-layer interconnection circuit moduleaccording to the present invention is directed to a method ofmanufacturing a multi-layer interconnection circuit module in whichplural unit wiring layers are interlayer-connected to each other througha large number of via holes so that they are laminated. In thismanufacturing method for multi-layer interconnection circuit module, thestep of forming respective unit wiring layers consists of a step offorming a first insulating layer by photosensitive insulating resinmaterial, a step of implementing photo-lithographic processing to thefirst insulating layer to form a large number of via hole groovescorresponding to respective via holes, a step of coating photosensitiveinsulating resin material onto the entire surface of the firstinsulating layer to form a second insulating layer as film, a step ofimplementing photo-lithographic processing to the second insulatinglayer to form wiring grooves corresponding to wiring patterns includingcommunicating portions with respective via hole grooves at a portionthereof, a step of filling conductive metal also within the respectivevia hole grooves and wiring grooves to form conductive metal layer asfilm on the entire surface of the second insulating layer, and a step ofpolishing the conductive metal layer until the principal surface of thesecond insulating layer is exposed. The respective via holes and thewiring patterns are formed by conductive metal filled within respectivevia hole grooves and wiring grooves of the conductive metallic layerexposed in such a manner to constitute the same surface on the principalsurface of the second insulating layer as the result of the fact thatpolishing processing has been implemented. In this manufacturing method,the unit wiring layer of the first layer is adapted so that the firstinsulating layer is formed as film on the base substrate, and the unitwiring layers of the upper layer are adapted so that respective firstinsulating layers are formed as film on the second insulating layer ofthe unit wiring layer of the lower layer.

In accordance with the manufacturing method for multi-layerinterconnection circuit module according to the present invention,photo-lithographic processing is implemented to the first and secondinsulating layers formed as film by photosensitive insulating resinmaterial to form via hole grooves and wiring grooves which have highresolution. From this fact, it becomes possible to form micro via holesand/or fine and high density wiring patterns. By using thismanufacturing method, respective unit wiring layers areinterlayer-connected to each other at the shortest distance byVia-on-Via structure so that they are laminated and formed to therebyshorten wiring length. As a result, attenuation of signals caused toundergo transmission is reduced, signal delay is minimized, and thinstructure can be realized. Thus, it is possible to manufacturemulti-layer interconnection (wiring) circuit module in which, e.g.,measure for large capacity, high speed and high density bus has beenrealized.

Still further objects of the present invention and practical meritsobtained by the present invention become more apparent from thedescription of the embodiments which will be given below with referenceto the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a longitudinal cross sectional view showing a conventionalcircuit module.

FIG. 2 is an essential part longitudinal cross sectional view showing acircuit module according to the present invention.

FIG. 3 is a longitudinal cross sectional view showing a formation stepfor first insulating layer.

FIG. 4 is a longitudinal cross sectional view showing a first exposurestep implemented onto the first insulating layer.

FIG. 5 is a longitudinal cross sectional view showing a firstdevelopment step implemented onto the first insulating layer.

FIG. 6 is a longitudinal cross sectional view showing a formation stepfor second insulating layer.

FIG. 7 is a longitudinal cross sectional view showing a second exposurestep implemented onto the second insulating layer.

FIG. 8 is a longitudinal cross sectional view showing a seconddevelopment step implemented onto the second insulating layer.

FIG. 9 is a longitudinal cross sectional view showing a formation stepfor conductive metal layer implemented onto the second insulating layer.

FIG. 10 is a longitudinal cross sectional view showing polishing step ofimplementing chemical-mechanical polishing processing to conductivemetallic layer.

FIG. 11 is a longitudinal cross sectional view showing multi-layerwiring circuit portion formed on base substrate.

FIG. 12 is a longitudinal cross sectional view showing a step ofmounting semiconductor chips onto multi-layer wiring circuit portion.

FIG. 13 is a longitudinal cross sectional view showing polishing step ofimplementing polishing processing to semiconductor chip and sealingresin layer.

BEST MODE FOR CARRYING OUT THE INVENTION

A multi-layer interconnection (wiring) circuit module (hereinaftersimply abbreviated as circuit module) and a manufacturing method thereofto which the present invention is applied will now be explained withreference to the attached drawings.

The circuit module according to the present invention has, e.g.,information communication function and/or storage function, etc., and ismounted in various electronic equipments such as personal computer,mobile telephone and/or audio equipment, etc., or constitutes a highfrequency circuit unit of micro communication function module bodyattached or detached as option. At the circuit module, although itsdetail is omitted, there is formed a high frequencytransmitting/receiving circuit unit based on the superheterodyne systemfor once performing conversion into intermediate frequency fromtransmit/receive signal, or a high frequency transmitting/receivingcircuit unit based on the direct conversion system for performingtransmission/reception of information signals without conductingconversion into intermediate frequency, etc.

As shown in FIG. 2, the circuit module 1 according to the presentinvention is composed of a multi-layer interconnection (wiring) circuitportion 2 having a first principal surface 2 a as a mounting surface andmounted through bumps 4 for mounting on a mother board 3, plural (two inFIG. 2) semiconductor chips (LSI) 6A, 6B mounted through a large numberof semiconductor mounting bumps 5 on a second principal surface 2 b ofthe multi-layer wiring circuit portion 2, and a sealing resin layer 7for sealing these semiconductor chips 6A, 6B. At the circuit module 1,the multi-layer wiring circuit portion 2 functions as interposer inwhich semiconductor chips 6A, 6B are mounted. It is to be noted that, atthe circuit module 1 according to the present invention, suitableelectronic parts (components) and/or element parts are also mounted onthe second principal surface 2 b of the multi-layer wiring circuitportion 2 although not shown.

In the circuit module 1 according to the present invention, themulti-layer wiring circuit portion 2 is constituted by five layerstructure as the result of the fact that a second unit wiring layer 9 islaminated and formed on the principal surface of a first unit wiringlayer 8 via steps which will be described later to laminate and form inorder a third unit wiring layer 10 to a fifth unit wiring layer 12 onthe principal surface of the second layer unit wiring layer 9 at timessubsequent thereto. In this circuit module 1, the multi-layer wiringcircuit portion 2 is interlayer-connected through via hole 13 formed ina manner penetrated through all layers, upper and lower layers or plurallayers of the first to five unit wiring layers 8 to 12. In addition, atthe circuit module 1, digital circuit networks in which fineness,miniaturization and high density have been realized are formed withinthe multi-layer interconnection (wiring) circuit portion 2 via stepswhich will be described later.

In the circuit module 1 according to the present invention, as describedlater, at the first to fifth unit wiring layers 8 to 12 of themulti-layer wiring circuit portion 2, there is provided the so-calledvia hole-on-via hole (Via-on-Via) structure in which via holes of theupper layer unit wiring layer side are directly formed on via holes ofthe lower layer unit wiring layer side. The circuit module 1 is mountedonto the mother board 3 so that supply of predetermined signals andpower is conducted from circuit portions of the mother board 3 side tothe multi-layer wiring circuit portion 2. Accordingly, in the circuitmodule 1 according to the present invention, the mother board 3 andsemiconductor chips 6A, 6B mounted on second principal surface 2 b ofthe multi-layer wiring circuit portion 2 are directly connected throughvia holes 13. Thus, shortening of wiring length is realized. In thiscircuit module 1, there is conducted connection in which attenuation oftransmission signals between the mother board 3 and the semiconductorchips 6A, 6B has been reduced, and connection in which signal delay hasbeen minimized.

In the circuit module 1 according to the present invention, as describedlater, polishing processing is implemented to the semiconductor chips6A, 6B and the sealing resin layer 7 to provide thin structure. Thus,thin structure of the entirety is realized. At the circuit module 1, asdescribed later, the multi-layer wiring circuit portion 2 is adapted sothat first unit wiring layer 8 is formed on a base substrate 20 providedwith a peeling layer 21 on planar principal surface, and second unitwiring layer 9 to fifth unit wiring layer 12 are formed in order on thefirst layer unit wiring layer 8 at times subsequent thereto. Themulti-layer wiring circuit portion 2 is peeled off from the basesubstrate 20 through the peeling layer 21 after undergone apredetermined step or steps. In this example, the base substrate 20 isre-used after processing such as rinse, etc. is implemented thereto.

At the circuit module 1 according to the present invention, themulti-layer wiring circuit portion 2 is adapted as described later sothat first unit wiring layer 8 is formed on base substrate 20 havingflat surface and unit wiring layers of the upper layer are formed inorder in the state where principal surfaces of the respective unitwiring layers including this first unit wiring layer 8 are flattened.Accordingly, the circuit module 1 is formed in the state whererespective wiring patterns of the first to fifth unit wiring layers 8 to12 is caused to have high accuracy and high density, and are caused tobe of thin structure. At the circuit module 1, as the result of the factthat the multi-layer wiring circuit portion 2 is caused to be of thinstructure, lengths of wirings which connects respective semiconductorchips 6A, 6B therebetween are further shortened.

At the circuit module 1, within the multi-layer wiring circuit portion2, capacitor elements 14, resistor elements 15 and/or inductor elements16 of the spiral type are formed as film by the thin film technology orthe thick film technology. The capacitor element 14 is, e.g., decouplingcapacitor or capacitor for cutting d.c. component, and is constituted bytantalum oxide (TaO) film or tantalum nitride (TaN) film. The resistorelement 15 is, e.g., resistor for termination resistor, and isconstituted by TaN film. At the circuit module 1, since first unitwiring layer 8 to fifth layer unit wiring layer 12 are formed in such amanner that they are laminated in order on the planar surface of thebase substrate 20 or the unit wiring layer of the lower layer asdescribed above, the capacitor elements 14, the resistor elements 15and/or the inductor elements 16 which have high accuracy are formed. Atthe circuit module 1, since passive elements such as the capacitorelement, the resistor element and/or the inductor element, etc. whichhave conventionally used chip parts are formed within the multi-layerwiring circuit portion 2, passive elements which are extremely small andhave high performance can be mounted in the state where wiring lengthsthereof has been shortened.

The circuit module 1 according to the present invention is manufacturedvia process steps which will be described later, and the first unitwiring layer 8 to the fifth layer unit wiring layer 12 are respectivelyconstituted by first insulating layer 22, second insulating layer 23 andconductive metal layer 24. In this manufacturing process for circuitmodule 1, manufacturing steps for the layer unit wiring layer 8 to thefifth layer unit wiring layer 12 respectively consist of a formationstep for via hole groove 25 which forms via hole 13 with respect to thefirst insulating layer 22, and a formation step for wiring groove 27 forforming wiring patterns 26 including, at a portion thereof,communicating portions with via hole groove 25 with respect to thesecond insulating layer 23. In the manufacturing process for circuitmodule 1, manufacturing processes for the first unit wiring layer 8 tothe fifth unit wiring layer 12 respectively consist of Cu plating stepof forming conductive metal layer 24 with respect to the secondinsulating layer 23, and Chemical-Mechanical Polishing (CMP) step ofpolishing conductive metal layer 24. In the manufacturing process forcircuit module 1, wiring patterns 26 and via holes 13 are formed via theabove-described steps within the first unit wiring layer 8 to the fifthunit wiring layer 12.

The manufacturing process for the circuit module 1 according to thepresent invention includes a semiconductor chip mounting step ofmounting semiconductor chips 6A, 6B onto the first principal surface 2 awith respect to the multi-layer wiring circuit portion 2 in which firstunit wiring layer 8 to fifth unit wiring layer 12 formed on the basesubstrate 20 via the above-described steps are laminated and formed, anda sealing resin layer formation step of sealing these semiconductorchips 6A, 6B by sealing resin layer 7. The manufacturing process for thecircuit module 1 includes a polishing step of simultaneously polishingthe semiconductor chips 6A, 6B and the sealing resin layer 7, and apeeling step of peeling the multi-layer wiring circuit portion 2 fromthe first base substrate 20 to manufacture the circuit module 1.

In the manufacturing process for the circuit module 1 according to thepresent invention, photo-lithographic process of high resolution isimplemented to the first insulating layer 22 and the second insulatinglayer 23 to form via hole grooves 25 and wiring grooves 27. Inaccordance with the manufacturing process for the circuit module 1, ascompared to the conventional manufacturing process of implementing holeprocessing for via hole and implementing patterning step using openingmask, wet type etching step or plating step, etc. to substrate on whichcopper foil layer is formed, there is formed circuit module 1 includingvia holes 13 and/or wiring patterns 26 which have high accuracy and highdensity and such that fineness and miniaturization have been realized.

As the result of the fact that the circuit module 1 according to thepresent invention is manufactured by the above-described manufacturingprocess steps, respective via holes 13 are formed at about several μmand in the state where they are very small and accurate at the firstunit wiring layer 8 to the fifth unit wiring layer 12, and respectivewiring patterns 26 are also formed to be extremely fine in such a mannerthat the pitch has several μm level. At the circuit module 1,micro-strip lines such that, e.g., the upper and lower layers are put byground therebetween are formed at the first unit wiring layer 8 to thefifth unit wiring layer 12 so that impedance-controlled wiring patterns26 are formed.

As compared to the circuit module manufactured by employing theconventional manufacturing method, the circuit module 1 manufactured bythe manufacturing method according to the present invention can bereduced down to about {fraction (1/10)} in terms of area size, and uselimit frequency band can be increased to 20 GHz. In the circuit module 1according to the present invention, the first layer unit wiring layer 8to the fifth layer unit wiring layer 12 which constitute the multi-layerwiring circuit portion 2 are formed in the state where thickness thereofis, e.g., about 5 μm, and the entire thickness of the multi-layer wiringcircuit portion 2 can be held down to about several ten μm. Since thesemiconductor chips 6A, 6B are polished precisely and at the maximum sothat they have thickness of about 100 μm, the circuit module 1 accordingto the present invention can be caused to be of thin structure to muchdegree.

Respective steps of the manufacturing method for the circuit module 1according to the present invention will be explained in detail withreference to FIGS. 3 to 12.

In the manufacturing process for circuit module 1 according to thepresent invention, base substrate 20 formed as shown in FIG. 3 isprovided first. The base substrate 20 is formed by substrate material,e.g., Si substrate, glass substrate or quartz substrate, etc. havinginsulating characteristic, heat-proof characteristic or chemicals proofcharacteristic, and mechanical rigidity and such that planar surface ofhigh accuracy can be formed. At the base substrate 20, by using suchbase material, thermal change is suppressed with respect to elevation ofsurface temperature at the time of sputtering processing which will bedescribed later, and holding of focal depth at the time ofphoto-lithographic processing and improvement in the contact alignmentcharacteristic are realized so that circuit module 1 of high accuracycan be manufactured. It is to be noted that the base substrate 20 is notlimited to the above-described base material, but other substratesuitable material to which planation processing has been implemented maybe used.

The base substrate 20 used for the manufacturing method of the presentinvention is adapted so that polishing processing is implemented to theprincipal surface 20 a to form the principal surface 20 a as planarsurface of high accuracy, and peeling layer 21 is formed as film on thisprincipal surface 20 a. The peeling layer 21 is composed of metallicthin film layer such as copper or aluminum, etc. formed in a mannerextending over the entirety with uniform thickness of about 10 μm on theprincipal surface 20 a of the base substrate 20 by, e.g., sputteringmethod or Chemical Vapor Deposition (CVD), etc. and a resin thin filmlayer such as polyimide resin, etc. having thickness of about 1 μm to 2μm formed on the entire surface by, e.g., spin-coat method, etc. on thismetallic thin film layer. In the peeling layer 21, at the peeling stepwhich will be described later, multi-layer wiring circuit portion 2 ispeeled off from the base substrate 20 with the first layer unit wiringlayer 8 being as peeling surface.

In the manufacturing process of the circuit module 1 according to thepresent invention, first unit wiring layer 8 is formed on the peelinglayer 21. In the manufacturing process for the first layer unit wiringlayer 8, as shown in FIG. 3, the first step is to form first insulatinglayer 22 as film on the peeling layer 21 of the base substrate 20. Asthe first insulating layer 22, e.g., negative type photosensitiveinsulating resin material of polyimide system or epoxy system is used.The first insulating layer 22 is formed as film over the entire surfacethereof on the peeling layer 21 by, e.g., spin-coat method, curtain coatmethod, roll coat method or dip-coat method which permits coatinguniformness characteristic or control characteristic. The firstinsulating layer 22 is formed as film on flat base substrate 20 throughflat peeling layer 21 so that it is formed with uniform thickness.

In the manufacturing process for the first unit wiring layer 8, thesecond step is to implement first photo-lithographic processing to formvia hole grooves 25 in correspondence with via holes 13 at firstinsulating layer 22. The first photo-lithographic processing includes,as shown in FIG. 4, processing for disposing first photo-mask 30 on thesurface of the first insulating layer 22 after undergone positioning,first exposure processing for exposing a predetermined portion of thefirst insulating layer 22 through the first photo-mask 30, and firstdevelopment processing for developing the first insulating layer 22. Asshown in FIG. 4, the first photo-mask 30 is comprised of sheet materialwhere there is formed light shielding/transmitting pattern in which theportion where via hole groove 25 corresponding to via hole 13 is to beformed is caused to be light shielding portion 30 a, and other portionis caused to be light transmitting portion 30 b, and is disposed on thesurface of the first insulating layer 22 in the state it is closelycontact therewith after undergone positioning.

In the first exposure processing, there is employed a suitable method,e.g., a method of irradiating laser beams caused to undergo operationcontrol in X-Y direction, or a method of irradiating outgoing light frommercury lamp, etc. As shown in FIG. 4, the first insulating layer 22 isselectively exposed by processing light L₁ transmitted from the lighttransmitting portion 30 b of the first photo-mask 30. At the firstinsulating layer 22, the portion except for the portion where via holes13 are formed as indicated by broken lines in FIG. 4 is selectivelyexposed over the entire area in the thickness direction by this firstexposure processing, and is changed into latent image. In the firstdevelopment processing, e.g., base substrate 20 to which the firstexposure processing has been implemented is immersed into alkalisolution to thereby remove, as shown in FIG. 5, unexposed portion of thefirst insulating layer 22, i.e., the portion where respective via holes13 are formed to form predetermined via hole grooves 25.

In the manufacturing process for the first unit wiring layer 8, thethird step is to form second insulating layer 23 as fim on the firstinsulating layer 22 where via hole grooves 25 are formed as shown inFIG. 6 is caused to be third step. Also as the second insulating layer23, similarly to the first insulating layer 22, e.g., negative typephotosensitive insulating resin material of polyimide system or epoxysystem is used. The second insulating layer 23 is formed as film withuniform film thickness over the entire surface on the first insulatinglayer 22 by, e.g., spin coat method, curtain coat method, roll coatmethod or dip-coat method, etc. which permits coating uniformcharacteristic or thickness control characteristic. As shown in FIG. 6,insulating resin material is filled also within via hole grooves 25formed at the first insulating layer 22 by the first step.

In the manufacturing process for the first unit wiring layer 8, thefourth step is to implement second photo-lithographic processing to formwiring grooves 27 in correspondence with wiring patterns 26 at thesecond insulating layer 23. The second photo-lithographic processingalso includes, as shown in FIG. 7, processing for disposing secondphoto-mask 31 on the surface of the second insulating layer 2, secondexposure processing for exposing a predetermined portion of the secondinsulating layer 23 through the second photo-mask 31, and seconddevelopment processing for developing the second insulating layer 23. Asshown in FIG. 7, the second photo-mask 31 is comprised of sheet materialwhere there is formed light shielding/light transmitting pattern inwhich the light shielding portion 31 a where wiring groove 27corresponding to wiring pattern 26 is to be formed is caused to be lightshielding portion 31 a and other portion is caused to be lighttransmitting portion 31 b, and is disposed on the surface of the secondinsulating layer 23 in the state where it is closely in contacttherewith after undergone positioning.

Also in the second exposure processing, the same exposure unit as theabove-described first exposure processing is used, and the secondinsulating layer 23 is selectively exposed by processing light L₂transmitted from the light transmitting portion 31 b of the secondphoto-mask 31. In the second exposure processing, as indicated by brokenlines in FIG. 7, the portion except for corresponding portion of thewiring pattern 26 is selectively exposed over the entire area in thethickness direction at the second insulating layer 23 to conductrealization of latent image. In the second development processing, e.g.,base substrate 20 to which the second exposure processing has beenimplemented is immersed into alkali solution to thereby remove, as shownin FIG. 8, unexposed portion of the second insulating layer 23, i.e.,corresponding portion of insulating resin material filled withinrespective via hole grooves 25 and patterns 26 to form, as pattern,wiring grooves 27 along with predetermined via hole grooves 25.

In the manufacturing process for the first unit wiring layer 8, thefifth step is to implement metal plating processing to the secondinsulating layer 23 in which via hole groove 25 and wiring groove 27have been formed to form, as film, conductive metal layer 24. As themetal plating processing, either electrolytic plating or electrolessplating may be employed. As shown in FIG. 9, conductive metal layer 24having a predetermined thickness is formed on the entire surface of thesecond insulating layer 23 in such a manner that conductive metal isfilled up to the inside of the wiring groove 27 along with the via holegrooves 25. As the metal plating processing, specifically copper platingis implemented to the conductive metal layer 24 for the purpose offorming copper film layer having excellent conductivity. In the casewhere conductive metal layer 24 is formed by electrolytic plating,peeling layer 21 is utilized as voltage application electrode.

In the manufacturing process for the first unit wiring layer 8, thesixth step is to polish the conductive metal layer 24 until theprincipal surface of the second insulating layer 23. In the polishingprocessing, a portion of the second insulating layer 23 is polishedalong with the conductive metal layer 24 to thereby form the principalsurface 8 a of the first unit wiring layer 8 so that it results in flatsurface as shown in FIG. 10. Since the second insulating layer 23 andthe conductive metal layer 24 which are different in material aresimultaneously polished, polishing processing is performed by CMP methodhaving polishing selectivity such that polishing rate of the conductivemetal layer 24 is increased.

In the manufacturing process for the first unit wiring layer 8, theabove-described polishing processing is implemented to therebymanufacture, as shown in FIG. 10, conductive metal which has been filledinto the via hole grooves 25 and the wiring grooves 27, i.e., firstlayer unit wiring layer 8 where copper layer is exposed in such a mannerto constitute the same surface as the second insulating layer 23 so thatvia holes 13 and wiring patterns 26 are respectively formed. At thefirst unit wiring layer 8, as described above, first insulating layer 22and second insulating layer 23 are formed with thickness of highaccuracy on the base substrate 20, and via holes 13 and wiring patterns26 are formed by via hole grooves 25 and wiring grooves 27 which havebeen formed as the result of the fact that the first and secondphoto-lithographic processing of high resolution have been implemented.

Accordingly, the first unit wiring layer 8 is constituted so as to be ofthin structure on the whole, but sufficient signal transmissioncharacteristic can be held because the wiring pattern 26 has thicknessequal to the thickness of the second insulating layer 23. At the firstlayer unit wiring layer 8, the via hole grooves 25 and the wiringgrooves 27 are formed at the first insulating layer 22 and the secondinsulating layer 23 in the state where they have high density, are fineand are miniaturized. Thus, via holes 13 and wiring patterns 26 in whichhigh density, fineness and miniaturization have been realized areformed. At the first unit wiring layer 8, although the detail isomitted, connection pads and/or input/output electrodes adapted to bemounted on mother board 3 are formed along with wiring pattern 26.

It is to be noted that while the first insulating layer 22 and thesecond insulating layer 23 are formed as film by negative typephotosensitive insulating resin material in the above-describedmanufacturing process for the first unit wiring layer 8, they may beformed as film by positive type photosensitive insulating resinmaterial. In such manufacturing process, the first and secondphoto-masks 30 and 31 are adapted so that portions corresponding to viahole grooves 25 and/or wiring grooves 27 are caused to be lighttransmitting portion, and other portions are caused to be lightshielding portion. In addition, in such manufacturing process, sinceexposure up to the first insulating layer 22 is conducted in the secondexposure processing, it is necessary to perform control of exposurequantity.

In the manufacturing process for circuit module 1, manufacturing processfor second unit wiring layer 9 is implemented onto the flattenedprincipal surface 8 a of the above-described first unit wiring layer 8.In the manufacturing process for second unit wiring layer 9, after firstinsulating layer 22 is formed as film on the principal surface 8 a ofthe first unit wiring layer 8, a step of implementing firstphoto-lithographic processing for forming the above-described via holegroove 25, a step of forming second insulating layer 23, a step ofimplementing second photo-lithographic processing for forming wiringgroove 27, a step of forming conductive metal layer 24, and a polishingprocessing are implemented. In the manufacturing process for secondlayer unit wiring layer 9, although the detail is omitted, passiveelements such as capacitor elements 14, resistor elements 15 and/orinductor elements 16, etc. are also formed by suitable method.

In the manufacturing process for circuit module 1, manufacturing processfor third unit wiring layer is implemented onto second layer unit wiringlayer 9 and steps of forming unit wiring layers of upper layers areimplemented in order at times subsequent thereto. Thus, as shown in FIG.11, multi-layer wiring circuit portion 2 is manufactured on the basesubstrate 20. At the multi-layer wiring circuit portion 2, as shown inFIG. 11, via holes 13 formed at the first unit wiring layer 8 to thefifth unit wiring layer 12 are adapted so that via holes of the upperlayer side are directly formed on via holes of the lower layer side toconstitute via hole-on-via hole structure. Accordingly, at themulti-layer wiring circuit portion 2, the first unit wiring layer 8 tothe fifth unit wiring layer 12 are connected with the shortest wiringlength. At the multi-layer wiring circuit portion 2, since unit wiringlayers of the upper layer are formed in order on unit wiring layers ofthe flattened lower layer, influence by accumulation of thickness ofwiring patterns of the lower layer side is suppressed so that the fifthunit wiring layer 12 of the uppermost layer is formed in the state wherewarp, waviness or uneven portion does not exist. Accordingly, at themulti-layer circuit portion 2, unit wiring layers of high accuracy arefurther formed on the fifth unit wiring layer 12 to permit highintegration.

In the manufacturing process for circuit module 1, as shown in FIG. 12,a step of mounting semiconductor chips 6A, 6B is implemented onto theprincipal surface of the fifth unit wiring layer 12 constituting thesecond principal surface 2 b of the multi-layer wiring circuit portion2. At the fifth unit wiring layer 12, although the detail is omitted,similarly to the wiring pattern 26, electrode pads for mountingsemiconductor chips 6A, 6B by suitable mounting method such as flip-chipmounting method, etc. and/or connection terminal portions for conductingconnection to other electronic parts or other modules, etc. are formed.In this example, e.g., electroless nickel/copper plating is implementedto electrode pad or connection terminal portion so that electrodeformation is performed. Although the detail is omitted, the step ofmounting semiconductor chip consists of a step of attaching mountingbump 5 onto electrodes of the semiconductor chips 6A, 6B, a step ofmounting the semiconductor chips 6A, 6B on the fifth unit wiring layer12 after undergone positioning, and a step of implementing, e.g., reflowsoldering processing, etc.

In the manufacturing process for the circuit module 1, as shown in FIG.12, a sealing step of sealing mounted semiconductor chips 6A, 6B bysealing resin layer 7 is implemented. The sealing resin layer 7 ismolded by transfer mold method or printing method, etc. by using resinmaterial having small thermal hardening contraction percentage, such as,for example, epoxy system resin, etc. so that generation of stress toproduce warp, etc. at the base substrate 20 or the multi-layer wiringcircuit portion 2 after hardening is suppressed.

In the manufacturing process for the circuit module 1, a step ofpolishing the semiconductor chips 6A, 6B and the sealing resin layer 7so that they have a predetermined thickness is implemented. Thepolishing step is conducted by, e.g., mechanical polishing method usinggrinder, chemical polishing method by wet etching, or CMP in whichmechanical polishing method and chemical polishing method are used incombination, etc., wherein the surfaces of the semiconductor chips 6A,6B are polished along with the sealing resin layer 7 within the maximumrange where there is no hindrance in function to thereby provide thinstructure as shown in FIG. 13. In the polishing step, the semiconductorchips 6A, 6B are polished in the state where they are sealed by sealingresin layer 7 with the base substrate 20 being as a supporting substrateto thereby conduct polishing at the maximum and precisely in such amanner that damage such as edge defect, etc. does not take place atrespective semiconductor chips 6A, 6B.

In the manufacturing process for the circuit module 1, although thedetail is not provided herein, after second base substrate includingpeeling layer is connected (bonded) to the sealing resin layer 7 towhich polishing processing has been implemented, a step of peelingcircuit module 1 from the base substrate 20 is implemented. The secondbase substrate constitutes a base in forming electrode pads at the firstunit wiring layer 8 which constitutes the first principal surface 2 a ofthe multi-layer wiring circuit portion 2 or implementing planationprocessing for the purpose of mounting circuit module 1 onto the motherboard 3, etc.

In the base substrate peeling step, the base substrate 20 where thecircuit module 1 has been formed via the above-described steps isimmersed into acid solution, e.g., hydrochloric acid, etc. At thecircuit module 1, peeling proceeds at the surface between the metallicthin film layer and the resin thin film layer of the peeling layer 21within the acid solution, and the circuit module 1 is peeled off fromthe base substrate 20 in the state where the resin thin film layer isleft at the first unit wiring layer 8 side. It is to be noted that thepeeling step may be adapted to implement, e.g., laser abrasionprocessing to thereby peel off the circuit module 1 from the basesubstrate 20. In addition, resin thin film layer left at the first unitwiring layer 8 side is removed by, e.g., dry etching method by oxygenplasma, etc.

An electrode formation processing to form Au—Ni layer by electrolessplating on the surfaces of connection pads and/or input/output terminalsformed at the first unit wiring layer 8 exposed to the first principalsurface 2 a is implemented to the multi-layer wiring circuit portion 2.The circuit module 1 is mounted in such a manner that mounting bump 4 isattached to the connection pad and reflow soldering is implemented inthe state where it has been caused to undergo positioning at the motherboard 3. In this example, at the circuit module 1, prior to the step ofmounting the mother board 3, a step of peeling off the second basesubstrate is implemented.

While the step of manufacturing one circuit module 1 on the basesubstrate 20 has been explained in the above-described manufacturingprocess for circuit module 1, relatively large base substrate 20 may beused to collectively manufacture a large number of circuit modules 1. Inthe manufacturing process for circuit module 1, in this case, cuttingprocessing for connecting portion which separates respective circuitmodules 1 is implemented prior to the peeling step from the basesubstrate 20. In addition, while circuit module 1 is manufactured onbase substrate 20 comprised of Si substrate or glass substrate in themanufacturing process for the circuit module 1, e.g., various organicsubstrates used in general manufacturing process for multi-layersubstrate to which planation processing has been implemented may beused.

While the circuit module 1 according to the present invention is causedto be of the configuration in which the multi-layer wiring circuitportion 2 also has an interposer which mounts semiconductor chips 6A,6B, it is a matter of course that such circuit module may be used assingle multi-layer wiring circuit module. In addition, it is a matter ofcourse that the. circuit module 1 may be adapted so that semiconductorchips and/or mounting parts may be mounted also at the principal surface2 a side of the multi-layer wiring circuit portion 2. At the circuitmodule 1, in this case, planation processing is implemented also to thefirst principal surface 2 a side with the second base substrate being asbase.

While the invention has been described in accordance with certainpreferred embodiments thereof illustrated in the accompanying drawingsand described in the above description in detail, it should beunderstood by those ordinarily skilled in the art that the invention isnot limited to the embodiments, but various modifications, alternativeconstructions or equivalents can be implemented without departing fromthe scope and spirit of the present invention as set forth and definedby the appended claims.

Industrial Applicability

As described above, in the present invention, respective unit wiringlayers are adapted so that photo-lithographic processing is implementedto first insulating layer formed by photosensitive insulating resinmaterial to form via hole grooves, and photo-lithographic processing isimplemented to second insulating layer formed by photosensitiveinsulating resin material on the first insulating layer to form wiringgrooves to implement polishing processing to the conductive metal layerformed on the second insulating layer so that conductive metal is filledinto the via hole grooves and the wiring grooves until the principalsurface of the second insulating layer is exposed to form via holes andwiring patterns by the conductive metal filled within the via holegrooves and the wiring grooves. Accordingly, micro and fine via holesand/or wiring patterns are formed at high density by photo-lithographicprocessing of high resolution so that miniaturization and thin structureare realized. In accordance with the present invention, since respectiveunit wiring layers are interlayer-connected at the shortest distance byvia-on-via structure, attenuation of transmission signals based onshortening of wiring length is reduced, delay of transmission isminimized, and influence of noise is also reduced. Thus, improvement inreliability is realized, and countermeasure of large capacity, highspeed and high density bus can be realized.

1. A multi-layer interconnection circuit module in which plural unitwiring layers are interlayer-connected to each other through a largenumber of via holes so that they are laminated and formed, wherein therespective unit wiring layers are composed of a first insulating layerformed as film by photosensitive insulating resin material and such thatphoto-lithographic processing is implemented thereto so that a largenumber of via hole grooves corresponding to the respective via holes areformed, a second insulating layer formed as film by photosensitiveinsulating resin material on the first insulating layer, and such thatphoto-lithographic processing is implemented so that wiring groovescorresponding to wiring patterns including communicating portions withthe respective via hole grooves at a portion thereof are formed aspattern, and a conductive metal layer formed as film on the secondinsulating layer as the result of the fact that conductive metal isfilled also within the respective via hole grooves and the wiringgrooves, whereon polishing processing is implemented until the principalsurface of the second insulating layer is exposed so that the respectivevia holes and the wiring patterns are formed by the conductive metalfilled within the respective via hole grooves and the wiring grooves ofthe exposed conductive metal layer in such a manner to constitute thesame surface on the principal surface of the second insulating layer. 2.The multi-layer interconnection circuit module as set forth in claim 1,wherein the first insulating layer and the second insulating layer areformed as film by negative type photosensitive insulating resinmaterial.
 3. The multi-layer interconnection circuit module as set forthin claim 1 wherein polishing processing by the chemical-mechanicalpolishing method is implemented to the conductive metal layer.
 4. Themulti-layer interconnection circuit module as set forth in claim 1,wherein the conductive metal layer is copper film layer formed by copperplating.
 5. The multi-layer interconnection circuit module as set forthin claim 1, wherein the unit wiring layer of the lowermost layer isformed on base substrate including peeling layer formed as film on flatprincipal surface, and is peeled through the peeling layer after apredetermined layer is laminated and formed.
 6. The multi-layerinterconnection circuit module as set forth in claim 1, wherein ICchips, LSIs, and/or mounting parts are mounted on the unit wiring layerof the uppermost layer.
 7. A method of manufacturing a multi-layerinterconnection circuit module in which plural unit wiring layers areinterlayer-connected to each other through a large number of via holesso that they are laminated and formed, the step of forming therespective unit wiring layers comprising a step of forming a firstinsulating layer by photosensitive insulating resin material, a step ofimplementing photo-lithographic processing to the first insulating layerto form a large number of via holes corresponding to the respective viaholes, a step of coating photosensitive insulating resin material ontothe entire surface of the first insulating layer to form a secondinsulating layer as film, a step of implementing photo-lithographicprocessing to the second insulating layer to form wiring groovescorresponding to wiring patterns including communicating portions withthe respective via hole grooves at a portion thereof, a step of fillingconductive metal also within the respective via hole grooves and thewiring grooves to form, as film, conductive metal layer on the entiresurface of the second insulating layer, and a step of polishing theconductive metal layer until the principal surface of the secondinsulating layer is exposed, wherein the polishing processing isimplemented so that the respective via holes and the wiring patterns areformed by the conductive metal filled within the respective via holegrooves and the wiring grooves of the exposed conductive metal layer insuch a manner to constitute the same surface on the principal surface ofthe second insulating layer, and wherein the unit wiring layer of thefirst layer is adapted so that the first insulating layer is formed asfilm on base substrate, and the unit wiring layers of upper layer areadapted so that the respective first insulating layers are formed asfilm on the second insulating layer of the unit wiring layer of lowerlayer.
 8. The method of manufacturing multi-layer interconnectioncircuit module as set forth in claim 7, wherein the photosensitiveinsulating resin material used at the step of forming first insulatinglayer and the step of forming second insulating layer is negative typephotosensitive insulating resin material.
 9. The method of manufacturingmulti-layer interconnection circuit module as set forth in claim 7,wherein polishing step with respect to the conductive metal layer ispolishing processing by chemical-mechanical polishing method.
 10. Themethod of manufacturing multi-layer interconnection circuit module asset forth in claim 7, wherein the step of forming conductive metal layeron the respective second insulating layers is a step of implementingcopper plating to form copper film layer.
 11. The method ofmanufacturing multi-layer interconnection circuit module as set forth inclaim 7, wherein the step of forming the unit wiring layer of firstlayer is conducted on a base substrate where peeling layer is formed asfilm on the flat principal surface thereof, the method including a stepof forming the unit wiring layer of a predetermined layer thereafter topeel it through the peeling layer.
 12. The method of manufacturingmulti-layer interconnection circuit module as set forth in claim 7, themethod including a step of mounting IC chips, LSIs and/or mounting partsonto the unit wiring layer of the uppermost layer.